Numbers

In digital circuits, numbers are implemented in binary notation and all mathematical operations - addition, subtraction, comparison, multiplication, division or modulo - are performed by manipulating bits.

Example: Even or Odd Number

We will design a circuit that receives a 4-bit input number and activates the output ( $P a r e l l = 1$ ) when the input number is even.

A binary number is even if its least significant bit (LSB) has the value 0.

We define the input variable:

n o m b r e [3 : 0] = [n o m b r e_{3} n o m b r e_{2} n o m b r e_{1} n o m b r e_{0}]

The least significant bit is $n o m b r e_{0}$ .

The output is a single bit:

$P a r e l l = 1$ if the number is even.
$P a r e l l = 0$ if the number is odd.

Partial example table (the complete one would have 16 rows):

$n o m b r e$	Number in decimal	$n o m b r e_{0}$ (LSB)	Parity	$P a r e l l$
0000	0	0	Even	1
0001	1	1	Odd	0
0010	2	0	Even	1
0011	3	1	Odd	0
1110	14	0	Even	1
1111	15	1	Odd	0

Building the circuit is fairly straightforward; the output Parell must be activated (value 1) if and only if nombre[0] has the value 0, regardless of the value of the remaining bits of nombre.

Therefore, the output is the negation of $n o m b r e_{0}$ .

P a r e l l = \overset{―}{n o m b r e_{0}}

Thus, only a single NOT gate is required.

Example: Modulo 7 of a 4-bit number

We will design a circuit that computes the modulo 7 of a binary number $n$ , of 4 bits. Computing modulo 7 of a number consists of finding the remainder when it is divided by 7. The notation for this operation is:

r e s i d u = n mod 7

A 4-bit number $n [3 : 0] = [n_{3} n_{2} n_{1} n_{0}]$ can take 16 different values from 0000 to 1111 (0 to 15 in decimal).

The remainders after dividing a number by 7 can take values from 0 to 6. To represent the result of the operation, a 3-bit number will suffice, which can take values from 000 to 111 (0 to 7 in decimal).

r e s i d u [2 : 0] = [r e s i d u_{2} r e s i d u_{1} r e s i d u_{0}]

The first step in designing this circuit is to create the complete truth table that relates each 4-bit input $n [3 : 0]$ to its corresponding 3-bit remainder $r e s i d u [2 : 0]$ .

$r e s i d u [2 : 0] = n [3 : 0] \mod 7$

$n$ (decimal)	$n_{3} n_{2} n_{1} n_{0}$	$r e s i d u$ (decimal)	$r e s i d u_{2} r e s i d u_{1} r e s i d u_{0}$
0	0000	0	000
1	0001	1	001
2	0010	2	010
3	0011	3	011
4	0100	4	100
5	0101	5	101
6	0110	6	110
7	0111	0	000
8	1000	1	001
9	1001	2	010
10	1010	3	011
11	1011	4	100
12	1100	5	101
13	1101	6	110
14	1110	0	000
15	1111	1	001

For each output ( $r e s i d u_{0}$ , $r e s i d u_{1}$ , $r e s i d u_{2}$ ) a Karnaugh map with 4 variables is built to obtain its simplified Boolean expression.

Output $r e s i d u_{0}$

We construct the Karnaugh map for the 4 input variables for the output residue_0 and identify 3 groups.

n1 n0 n3 n2	01	11
00	1	1
01	1	1
11	1	0
10	1	1

n1 n0 n3 n2	01	11
00	1	1
01	1	1
11	1	0
10	1	1

The simplified Boolean expression for residue_0 will have 3 terms:

r e s i d u_{0} = \overset{―}{n_{1}} n_{0} + \overset{―}{n_{3}} n_{0} + \overset{―}{n_{2}} n_{0}

Output $r e s i d u_{1}$

We build the Karnaugh map for the 4 input variables for the output residue_1 and identify 2 groups.

n1 n0 n3 n2	11	10
00	1	1
01	1	1
11	0	0
10	1	1

n1 n0 n3 n2	01	11	10
00	0	1	1
01	0	1	1
11	0	0	0
10	1	1	0

Aquesta expressió booleana simplified for residue_1 tindrà 2 termes:

r e s i d u_{1} = \overset{―}{n_{3}} n_{1} + \overset{―}{n_{2}} n_{1}

Output $r e s i d u_{2}$

For the output residue_2, identify 2 groups on its Karnaugh map.

n1 n0 n3 n2	00	01	11	10
00	0	0	0	0
01	1	1	1	1
11	1	1	0	0
10	0	0	0	0

en | 1 | | 1111 | 15 | 1 | Odd | 0 |

n1 n0 n3 n2	00	01	11	10
00	0	0	0	0
01	1	1	1	1
11	1	1	0	0
10	0	0	1	1

Thus, the simplified Boolean expression for residue_2 will have 2 terms:

r e s i d u_{2} = n_{2} \overset{―}{n_{1}} + \overset{―}{n_{3}} n_{2}

From these three expressions we can use logic gates to create the digital circuit that will implement the function $n mod 7$ .

Exercises on Jutge.org: [Introduction to Digital Circuit Design]

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